Apparatus for multiple-error correcting codes

ABSTRACT

WHEREIN I is the identity element and A1, A2,...AK are distinct nonzero elements of Galois Field (2b), wherein the indicated multiplication and addition are the Galois Field defined operations, and wherein b is an integer &gt; 1, and K is an integer 2 &lt; K &lt; 2b.   Apparatus including an encoder adapted for encoding blocks of data into a sent message and a decoder adapted for recovering the data from a received message corresponding to the sent message but which may be in error wherein the blocks of data consist of K-bytes of data (D1, D2,...DK) each of b bits. The sent message comprises the K-bytes of data plus two check bytes C1 and C2, each of b bits. The decoder is effective in recovering the data without error when not more than a single byte of the received message is in error no matter how many bits may be in error in the single byte. The encoder computes the check bytes according to the relationships

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[72] Inventor Douglas (J. lilosaen Wappingers Falls, N11. [21] Appl. No.110,847 [22] Filed Feb. 112, 119711 [45] Patented Dec. 21,1971 [73]Assignee International Business Machine-a Corporation Armonk, NY.

[54] APPARATUS FOR MULTIPLE-ERROR v CORRECTING CODES 7 Claims, 9 DrawingFigs.

[52] US. [Cl Mil/11613.11 [SI] Int. Cl .filhfililll/IZ, G08c 25/00 [50]Field ol Search IMO/146.1; 235/153 [56] References Cited UNITED STATESPATENTS 3,418,630 12/1968 Van Duuren 340/1461 3,458,860 7/1969Shimabukuro IMO/146.1 3,474,413 10/1969 Dryden Primary Examiner-CharlesE. Atkinson Attorneysl-1Ianitin and Jancin and Harold I-l. Sweeney, Jr.

AMS'TIRAC'II: Apparatus including an encoder adapted for encoding blocksof data into a sent message and a decoder adapted for recovering thedata from a received message corresponding to the sent message but whichmay be in error wherein the blocks of data consist of lK-bytes of data(D D ,...D each of b bits. The sent message comprises the 1(- bytes ofdata plus two check bytes C, and C each of b bits. The decoder iseffective in recovering the data without error when not more than asingle byte of the received message is in error no matter how many hitsmay be in error in the single byte. The encoder computes the check bytesaccording to the relationships wherein I is the identity element and A A,...A are distinct nonzero elements of Galois Field (2), wherein theindicated multiplication and addition are the Galois Field definedoperations, and wherein b is an integer 1, and K is an integer 2 K 2".

PATENH-Znnmmn E 3.629324 SHEET 1 BF 7 L 7T ENCODER PROCESSOR DECODERDATA 2 RECEIVED SENT MESSAGE RECOVERED MESSAGE DATA RECEIVED FIG. 2MESSAGE 12 U l 4 2 COMPUTER COMPUTER x BJ COMPUTER \22 ERROR 2 RECOVEREDCORRECT um 6/ was PATENTEU BEBE] I971 SHEET 5 BF 7 PATENTEUHEEZI mBLGZQLBEA SHEET 5 [IF 7 1 P B M AND AND AND APPARATUS FOR MULTIPLE-ERRORCORRECTING CODES This invention relates to error-correcting codes. Aprimary object of the invention is to effect error-free recovery ofdata. Other objects are to correct one or more errors within a singlemultiple-bit byte of data and to effect such recovery and correctionwith a low-redundancy code and a minimum of apparatus. For example, in asystem where data is recorded by punching eight binary bits of data intoindividual cards (each considered as a byte), the invention will efiecterror-free recovery of the data from a block of cards when several bitsof data from a single card are erroneously punched.

The invention features apparatus including an encoder adapted forencoding blocks of data into a sent message and a decoder adapted forrecovering the data from a received message corresponding to the sentmessage but which may be in error, wherein the blocks of data consist ofK-bytes of data (D,, D ,...D each of b bits, the sent message comprisesthe K-bytes of data plus two check bytes C, and C each ofb bits, thedecoder is effective in recovering the data without error when not morethan a single byte of the received message is in error no matter howmany bits may be in error in the single byte, and the encoder computesthe check bytes according to the relationships wherein I is the identityelement and A,, A ,...A,,- are distinct nonzero elements of Galois Field(2), wherein the indicated multiplication and addition are the GaloisField defined operations, and wherein b is an integer 1, and K is aninteger 2 K 2".

Preferred embodiments feature means including a plurality of modulo-2adder circuits for concurrent computation of syndrome bytes S, and Saccording to the relationships S =A,D,+A D ...+A,,D,,'+IC (wherein aprimed symbol indicates a byte of the received message corresponding tothe unprimed symbol in the sent message), means including a plurality ofadder circuits and an OR circuit for calculating correction criteriaaccording to the relationship B,=A,-S,+IS the condition B O indicatingcorrection in the j" byte of the received message, and means forcorrecting any byte of the received message including for each bit ofreceived data d (designating the p' bit of the j'" byte) three ANDcircuits, the first having as inputs d, and S, (designating the negativeof the p" bit of the j" syndrome byte the second having as inputs 11 andB, (designating the correction criterion of thej'" byte), and the thirdhaving as inputs 1],, and S, by which means S, is added to the j" byteof the received message when the j' criterion indicates a correction.

Other objects, features, and advantages will appear from the followingdescription of a preferred embodiment of the invention taken togetherwith the attached drawings thereof, in which FIG. 1 shows a blockdiagram of a data handling system using the invention;

FIG. 2 shows a block diagram of the decoder according to the invention;

FIG. 3 shows the organization of the encoder according to the invention;

FIG. 4 shows the organization of the syndrome computer;

FIGS. 5a and 5b show the organization of the criteria computer;

FIG. 6 shows the organization of the correction computer;

FIG. 7 shows the encoding matrix; and

FIG. 8 shows the decoding matrix.

Referring to FIG. II, data enters an encoder 1 through a channel 2.Encoder 1 generates a sent message which passes through channel 3 to aprocessor 4 which performs some operation on the message, for example,storing it and subsequently reactivating it, and then transcribes areceived message which passes through channel Stodeooderfi which decodesthe received message and emits recovered data, which passes throughchannel 7 to some further use. The operation of processor 4 may beimperfect and make occasional errors so that the received message inchannel 5 is not necessarily identical with the sent message in channel3. The encoder l and decoder 6 cooperate to emit recovered data atchannel 7 having fewer errors than are made by the processor.

It will be appreciated by those skilled in the art that this inventioncan be applied to information-handling systems of various capacities.The invention will, therefore, be first described in algebraic termswhich are applicable to any size system and subsequently in terms of aspecific system.

According to the invention, data is processed by the system in blocksconsisting of K-bytes, each byte having b bits of data. (Here andthroughout, b designates an integer l and K an in teger 2 K 2". Thevalues of b and K are to be considered invariant for a particularembodiment, but are variously chosen for embodiments of variouscapacities.) A block of data will accordingly be designated D,, D,...D,,- wherein D, represents the first byte in the block, D the secondbyte, and so on to D,,' which represents K' and last byte. Arepresentative byte of data will be designated D,- with the subscriptjassuming any integral value l fgK. According to the invention, theencoder calculates from the block ofdata two check bytes, (designated C,and C each ofb bits and appends the check bytes of the K data bytes togenerate the sent message of [(+2 bytes.

In order to describe the calculation of the check bytes it is convenientto note that for bytes composed of b binary bits there are 2 distinctbytes possible and to regard each possible byte as an element of aGalois Field of 2 elements (or GF(2")). The existence of GF( 2") isassured for any value ofh by general theorems of algebra. (See forexample W. Wesley Peterson: Error Correcting Codes; M.I.T. Press (l96lThe Galois Field implies two operations conventionally designatedaddition with the corresponding zero element 6, and multiplication" withcorresponding identity element I. The terms addition and multiplicationand related terms such as adder will be used in this sense throughout.

The rules of addition and multiplication of bytes are established byrecognizing that the GF (2") of possible bytes is isomorphic with theGF(Z") of polynomials with coefficients in GF(2) taken modulo anirreducible polynomial of degree b. (At least one irreducible polynomialexists for any b.) The field of such polynomials is a vector space ofdimension b over GF(2). Addition of the elements in GF(2") is thereforeaccomplished by addition of corresponding bits. (Addition is of coursein GF(2) and thus equivalent to addition modulo 2.) Multiplication inGF( 2") can be thought of as defining a set of linear transformations inthe corresponding vector space of dimension b. it

The vector space is spanned by the column vectors:

matrix T where the vector and matrix components are in GF(2). (i.e.,binary bits). These operations will be illustrated below in connectionwith a preferred embodiment.

Returning now to the data handling system, according to the invention,the encoder calculates the check bytes according to the relationshipsC,=ID,+TD ...+ID (4) C A D,+A D ...+A D 5 where A,, A ...A,,- aredistinct, nonzero elements, of GF(2). Since there are 2-l such elements,the number of bytes in a block is limited to K 2". It is convenient toexpress the relationships by which C and C are computed by an encodingmatrix giving the coefficients I I. I

and the encoding calculation can be written symbolically C=H D Employingthe relationships developed above, the encoding matrix can be expressedin binary form by replacing each element of GF(Z") appearing in theencoding matrix by the corresponding binary multiplication matrix. Theresulting form of the encoding matrix will give explicitly theoperations to be performed by a binary-based computer to calculate thecheck bytes. 7

Turning now to the decoding, the decoder 6 receives a received message0,, D 'mD C C of K+2 bytes and matrices.

The significance of the syndrome (5,, S can be understood fromconsideration of the following operations which can be readily derivedfrom the encoding and decoding relationships on the supposition that atleast all but one byte has been correctly transcribed. lf S,=0, S =6,there is no error in the received message. lfS,=6, S 149, there is anerror in C lf S,9, S =0, there is an error in C If S =A,-S 0, there isan error of S in D v 1 A The decoder generates for every byte acriterion from the equation B,=A,-S,+IS

(l2) and generates the recovered data D," according to J" J' fl 1 J'+-Si(@1 11.14). in particular it should be recognized that the byte in erroris corrected even if multiple bits within the byte are in error.

Referring now to FIG. 2 showing a block diagram of a preferredembodiment handling a data block of 64 bits in 8 bytes, each of 8 bits,the received message enters decoder 6 at 12 and passes in parallelchannels to first syndrome component computer 14, second syndromecomponent computer 16. and error corrector 18. Computer 14 computes andemits at 20 syndrome component 8,, which passes by parallel channels toerror corrector l8 and criteria computer 22. Computer 16 computes andemits at 21 syndrome component S which passes to criteria computer 22.Criteria computer 22 calculates criteria B, for every D and emits thecriteria at 24 where they pass to error corrector 18. Error corrector l8calculates the recovered data D and emits them at 26.

H6. 3 shows the organization of the encoder. The data enters at 30 andis fanned out to eight adders 32-1 to 32-8 calculating C and eightadders 34-1 to 34-8 calculating C The output of each adder is the sum ofits inputs, the addition being defined in GF(2). in FIG. 3 the data isshown in binary form as it is processed by a binary-based machine. d,representing the p'" bit of the j" byte.

The fanning scheme is according to the general principles describedabove. For thepreferred embodiment, the eightand the multiplicationmatrices are based on the irreducible P9 "l *i iif?fixif r519%- Theresulting encoding matrix is shown in binary form in FIG.

I The bit inputs 36 to adder 32-1 which calculates the first bit ofcheck byte C are shown in full in FIG. 3. These inputs correspond to thefirst row of H Similarly the inputs 38 to adder 34-2 calculating the 2'bit of the 2" check byte are shown. These correspond to the row of H Theother inputs not shown in detail can be obtained by reference to H FIG.4 shows the organization of syndrome computers 14,

16 of decoder 6. The received message enters at 12 and fans out to theadders 42-1 to 42-8 which calculate the bits of the first syndromecomponent S, and to the adders 444 to 44-8 calculating the bits of thesecond component S in accordance with the decoding matrix expressed inbinary form as shown in 1 FIG. 8. The individual inputs are shown foradder 42-1 and i the input for others (not shown in detail in FIG. 4)can be obtained from Hp. The top eight rows of H are used to compute Sand the bottom eight to compute S The organization of the criteriacomputer is shown in FIGS. 5a and 5b. Syndrome bits (the third bit ofthe second syn- Outputs B B mB are obtained from similar circuitry. Thesyndrome bits fed to each adder are indicated in FIGS. and

A typical portion or error corrector 18 is shown in FIG. 6, viz: thecircuits which process the p' bit of the 1'' byte. Three AND-circuits61, 62, 63 are used in parallel feeding into OR- circuit 64. Threeinverters 65, 66, 67 are included. AND-circuit 61 has as inputs thereceived data bit d, and the syndrome bit S (where the bar indicates aninverted signal); AND-circuit 62 has as inputs the received data bit dand one of the correction criteria B}; AND-circuit 63 has as inputs thecorrection criterion inverted E, the received data bit inverted d andthe syndrome bit S OR-circuit 64 generates drome component is designatedS for example) are fed into 5 eight adders 52 according to equation(12). The output of the eight adders is fed to OR-circuit 54 whichproduces output 8,. v

the recovered data bit d, An identical group of circuits is provided foreach data bit, so that in all there are in general b times K groups (atotal of 641 in the preferred embodiment) of circuits as here describedin error corrector 118.

What is claimed is:

l. Apparatus including an encoder adapted for encoding blocks of datainto a sent message and a decoder adapted for recovering said data froma received message corresponding to said sent message but which may bein error, wherein said blocks of data consist of K-bytes of data (D,,D,...D,,-)

each of b bits, said sent message comprises said K-bytes of data plustwo check bytes C and C each of b bits, said decoder is effective inrecovering said data without error when not more than a single byte ofsaid received message is in error no matter how many bits may be inerror in said single byte, means in said encoder for computing saidcheck bytes according to the relationships c,=11).+m ...+m,.- C =A,D +AD ...+A D wherein I is the identity element and A A UA, are distinctnonzero elements of Galois Field (2), wherein the indicatedmultiplication and addition are the Galois Field defined operations, andwherein b is an integer 1, and K is an integer .2 I( 2. 1 2. Theapparatus of claim 11 including means in said decoder for computing twosyndrome bytes S and S each of 11 bits ac- 'cording to therelationships:

S,=ID,+ID '...+ID,"+IC S =A D +A D '...+A D -HC wherein a primed symbolindicates a byte of said received message corresponding to unprimedsymbol in said sent message.

3. The apparatus of claim 2 including; means in said decoder forgenerating correction criteria in response to syndrome bytes S and Saccording to the relationship E A ,S +15 the condition B =0 indicating acorrection on the j" byte of said received message.

4. The apparatus of claim 3 including means in said decoder forcorrecting any byte of said received message by adding syndrome S to thej' byte of said received message when the j"' said correction criterionindicates a correction.

5. The apparatus of claim 2 in which said means for computation of saidsyndrome bytes S and 8 includes a plurality of adder circuits wherebyall bits of both syndrome bytes S 1 and S are concurrently computed.

6. The apparatus of claim 3 in which said means in said decoder forgenerating each said correction criterion 8,- includes a plurality ofadder circuits for receiving said syndrome bytes S and S and adding themmodulo 2 in accordance with the modulo 2 additions indicated by saidequation B =A S I8 and an OR circuit having an input connection to theoutput of each of said adder circuits in accordance with the ORoperation indicated by said equation, the output of said OR circuitproviding said correction criterion 8,.

7. The apparatus of claim 4 in which :said means for correcting any byteof said received message includes for each bit of received data d(designating the p'" bit of the j"' byte) three AND circuits, the firstof said AND circuits having as inputs 11 and S (designating the negativeof the p bit of the first syndrome byte), the second of said ANDcircuits having as inputs d and the j" correction criterion 8,, and thethird of said AND circuits having as inputs 8,, d, and S December 23;3.91 1

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1. Apparatus including an encoder adapted for encoding blocks of datainto a sent message and a decoder adapted for recovering said data froma received message corresponding to said sent message but which may bein error, wherein said blocks of data consist of K-bytes of data (D1,D2...DK) each of b bits, said sent message comprises said K-bytes ofdata plus two check bytes C1 and C2, each of b bits, said decoder iseffective in recovering said data without error when not more than asingle byte of said received message is in error no matter how many bitsmay be in error in said single byte, means in said encoder for computingsaid check bytes according to the relationships C1 ID1+ID2...+IDK C2A1D1+A2D2...+AKDK wherein I is the identity element and A1, A2...AK aredistinct nonzero elements of Galois Field (2b), wherein the indicatedmultiplication and addition are the Galois Field defined operations, andwherein b is an integer >1, and K is an integer 2< K< 2b.
 2. Theapparatus of claim 1 including means in said decoder for computing twosyndromE bytes S1 and S2 each of b bits according to the relationships:S1 ID1''+ID2''...+IDK''+IC1''S2 A1D1''+A2D2''...+AKDK''+IC2'' wherein aprimed symbol indicates a byte of said received message corresponding tounprimed symbol in said sent message.
 3. The apparatus of claim 2including means in said decoder for generating correction criteria inresponse to syndrome bytes S1 and S2 according to the relationship BjAjS1+IS2, the condition Bj 0 indicating a correction on the jth byte ofsaid received message.
 4. The apparatus of claim 3 including means insaid decoder for correcting any byte of said received message by addingsyndrome S1 to the jth byte of said received message when the jth saidcorrection criterion indicates a correction.
 5. The apparatus of claim 2in which said means for computation of said syndrome bytes S1 and S2includes a plurality of adder circuits whereby all bits of both syndromebytes S1 and S2 are concurrently computed.
 6. The apparatus of claim 3in which said means in said decoder for generating each said correctioncriterion Bj includes a plurality of adder circuits for receiving saidsyndrome bytes S1 and S2 and adding them modulo 2 in accordance with themodulo 2 additions indicated by said equation Bj Aj S1+IS2 and an ORcircuit having an input connection to the output of each of said addercircuits in accordance with the OR operation indicated by said equation,the output of said OR circuit providing said correction criterion Bj. 7.The apparatus of claim 4 in which said means for correcting any byte ofsaid received message includes for each bit of received data dj,p''(designating the pth bit of the jth byte) three AND circuits, the firstof said AND circuits having as inputs dj,p'' and S1,p (designating thenegative of the pth bit of the first syndrome byte), the second of saidAND circuits having as inputs dj,p'' and the jth correction criterionBj, and the third of said AND circuits having as inputs Bj'', dj,p'' andS1,p.